1. Field of the Invention
This invention relates in general to microprocessor design and manufacture, and more particularly to an apparatus and method for testing memory circuits in a microprocessor.
2. Description of the Related Art
Two techniques are primarily employed to test memories in a microprocessor: the direct access technique and the built in self test (BIST) technique.
The direct access technique utilizes additional logic devices within the microprocessor to route all essential signals required for testing internal memories out to exterior pins on the operational package of the microprocessor. Thus, when the microprocessor is installed in a chip tester, the additional logic routes the address/data/control signals for a designated memory directly to external pins, thus bypassing internal circuitry that would otherwise preclude access to the signals. As a result, the chip tester is able to configure and execute any desired test sequence to detect defects in the designated memory. But, the additional logic devices, in order to route the signals to the external pins, are unavoidably designed directly into the primary internal path of the signals, thus introducing delays into both test mode operation and normal mode operation of the microprocessor. More precisely, the delays caused by additional direct access routing logic in the microprocessor prevent testing of its memories at full speed. But, more importantly, the delays slow down its normal operation. Consequently, while direct access testing provides the capability to configure virtually any test sequence, the inherent delays imposed by the additional logic slows down the normal operation of the device and allows a notable number of defects to go undetected, because the memories cannot be tested at full speed. Another negative side effect of the direct access method is that a large amount of (very expensive) chip tester vector memory is required to store the different data patterns that are required to write to and read from the memory array. An advantage of this method is that the chip tester is able to determine exactly which bits are bad or good. This is useful for memory array repair when the array is designed with redundant rows and/or columns.
The BIST technique directly interfaces dedicated test circuits, all within the microprocessor, to the essential memory signals so that each memory can be tested at full speed. More specifically, logic internal to the microprocessor is employed to test its memories. Address sequences and data patterns are programmed into BIST logic so that additional logic is not required to route the essential signals to a chip tester. But, while BIST logic provides for testing memories in a microprocessor at full speed, once it is designed into the microprocessor, its address sequences and data patterns are cast into stone, so to speak. Conventional BIST logic cannot be modified. To change a test sequence requires a design modification be made to the microprocessor. In contrast to the direct access method, BIST consumes very little chip tester vector memory, yet BIST only provides a rudimentary capability for a chip tester to determine exactly which bits of the memory array are good or bad. This BIST logic also consumes silicon area and power that is essentially wasted in normal use since it is only useful during chip manufacturing testing.
So, a microprocessor designer is forced to choose: should memory test configurability and ease of memory array repair be provided at the expense of full speed testing and a large amount of chip tester vector memory? Or, should full speed testing and small amount of chip tester vector memory be provided at the expense of memory test configurability and ease of memory array repair? One. skilled in the art will appreciate that all capabilities are required.
Therefore, what is needed is an apparatus in a microprocessor for testing memory that can test the memory at full speed, provide the capability to configure test parameters, provide the necessary data to allow memory array repair, and consume a small amount of chip tester vector memory. The apparatus must not inhibit full speed operation of the microprocessor when it is not testing memory.
In addition, what is needed is a configurable memory test apparatus within a microprocessor that can accept test parameters from a chip tester for the conduct of full speed tests on memories within the microprocessor.
Furthermore, what is needed is a microprocessor that can apply test parameters provided from a chip tester to a generic built in test sequence to form a specific test sequence for testing memory.
Moreover, what is needed is a method for testing memory in a microprocessor at full speed that can be configured to produce specific test sequences.
To address the above-detailed deficiencies, it is an object of the present invention to provide an apparatus for full speed testing of memory in a microprocessor that has the capability to configure test parameters, that provides the necessary information to properly repair the memory array, and consumes a relatively small amount of chip tester vector memory.
Accordingly, in the attainment of the aforementioned object, it is a feature of the present invention to provide an apparatus in a microprocessor for testing memory within the microprocessor. The apparatus includes test management logic and test execution logic. The test management accepts test parameters from a source external to the microprocessor and produces a specific test program using the test parameters. The test execution logic is coupled to the test management logic and executes the specific test program.
An advantage of the present invention is that full speed testing can be performed on memories in a microprocessor without having to sacrifice the ability to configure test sequences that were not originally designed into the device.
An additional advantage of the present invention is that information is collected during memory testing to facilitate memory array repair.
Another object of the present invention is to provide a configurable memory test apparatus within a microprocessor that can accept test parameters from a chip tester.
In another aspect, it is a feature of the present invention to provide an apparatus for testing memory in a microprocessor. The apparatus has a test controller, test management logic, and test execution logic. The test controller provides test parameters to the microprocessor to configure a specific test program. The test management logic is within the microprocessor and is coupled to the test controller. The test management logic accepts the test parameters and generates the specific test program. The test execution logic is within the microprocessor and is coupled to the test management logic. The test execution logic executes the specific test program.
Another advantage of the present invention is that chip tester programs, because they only pass test parameters to a microprocessor, are less complex and utilize less of the tester""s resources. Only a small amount of memory within a chip tester is required.
A further object of the invention is to provide a microprocessor that can apply test parameters provided from a chip tester to a generic built in test sequence to form a specific test sequence for testing memory.
In a further aspect, it is a feature of the present invention to provide an apparatus for testing a microprocessor. The apparatus includes a test controller, a test configuration register, a first sequence of micro instructions stored in a control ROM, and memory interface logic. The test controller provides test parameters to the microprocessor that prescribe a specific test to be performed. The test configuration register is located in the microprocessor and is coupled to the test controller. The test configuration register receives the test parameters. The first sequence of micro instructions stored in a control ROM is coupled to the test configuration register. The first sequence of micro instructions stored in a control ROM applies the test parameters to generate a second sequence of micro instructions that direct the microprocessor to execute the specific test. The memory interface logic is coupled to the control ROM, and accesses locations in the memory at full speed as prescribed by the second sequence of micro instructions.
A further advantage of the present invention is that test circuits in a microprocessor can be configured to test for heretofore unknown defects.
Yet another advantage of the present invention is that the present invention provides for testing of more potential failure modes than has heretofore been provided, without requiring design modifications to a microprocessor.
In yet another aspect, it is a feature of the present invention to provide a method for testing memory in a microprocessor at full speed. The method includes providing parametric data to the microprocessor that prescribes a specific memory test, applying the parametric data to a sequence of micro instructions within the microprocessor to form a specific sequence of micro instructions that direct the microprocessor to perform the specific memory test, and executing the specific sequence of micro instructions by the microprocessor. Execution of the specific sequence is performed at full speed.
Yet another advantage of the present invention is that the present invention provides for testing of more potential failure modes than has heretofore been provided, without requiring design modifications to a microprocessor.